[GCC newbie] Can't find any explanations about <UNDEFINED> or <UNPREDICTABLE> statements in list file
Hi @All,
first of all a short summary.
My company decided to go with a Spansion ARM Cortex M3 (MB9BF516N) and the GCC toolchain. Reason ist, that all of our former SOFTUNE Workbench source code can be easily ported (cause of Peripherial). As IDE we use Eclipse with the Kepler pulg-In.
After a few days now, I wrote a working Linker-Script & Startup-Files (they seem to be more stable the the ones from iSystems e.g. Atollic).
Compile an AS options are (Console Output):
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'Building file: ../source/
'Invoking: Cross ARM GNU Assembler'
arm-none-eabi-gcc -mcpu=cortex-m3 -march=armv7-m -mthumb -Os -fmessage-length=0 -ffunction-sections -fdata-sections -fno-common -fno-builtin -Wall -x assembler-with-cpp -I"..\1st_
'Finished building: ../source/
' '
'Building file: ../source/
'Invoking: Cross ARM C Compiler'
arm-none-eabi-gcc -mcpu=cortex-m3 -march=armv7-m -mthumb -Os -fmessage-length=0 -ffunction-sections -fdata-sections -fno-common -fno-builtin -Wall -I"..\1st_
'Finished building: ../source/
' '
.
.
.
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'Building target: 1st_test.elf'
'Invoking: Cross ARM C Linker'
arm-none-eabi-gcc -mcpu=cortex-m3 -march=armv7-m -mthumb -Os -fmessage-length=0 -ffunction-sections -fdata-sections -fno-common -fno-builtin -Wall -T "C:\PRG_
Using built-in specs.
COLLECT_
COLLECT_
Target: arm-none-eabi
Configured with: /home/build/
Thread model: single
gcc version 4.9.3 20141119 (release) [ARM/embedded-
COMPILER_
LIBRARY_
COLLECT_
c:/prg_dev/gnu tools arm embedded/4.9 2014q4/
c:/prg_dev/gnu tools arm embedded/4.9 2014q4/
c:/prg_dev/gnu tools arm embedded/4.9 2014q4/
.
.
.
c:/prg_dev/gnu tools arm embedded/4.9 2014q4/
'Finished building target: 1st_test.elf'
' '
make --no-print-
'Create Srec'
"C:\PRG_DEV\GNU Tools ARM Embedded\4.9 2014q4\
' '
'Invoking: Cross ARM GNU Create Listing'
arm-none-
'Finished building: 1st_test.lst'
' '
'Invoking: Cross ARM GNU Print Size'
arm-none-eabi-size --format=berkeley "1st_test.elf"
text data bss dec hex filename
31988 2172 2440 36600 8ef8 1st_test.elf
'Finished building: 1st_test.siz'
' '
10:40:34 Build Finished (took 19s.920ms)
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It works anyway after flashing the MCU. But in the listing file I dicovered a lot
of "<UNDEFINED> instruction" or <UNPREDICTABLE>.
see here:
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1st_test.elf: file format elf32-littlearm
1st_test.elf
architecture: arm, flags 0x00000102:
EXEC_P, D_PAGED
start address 0x00000101
Program Header:
0x70000001 off 0x0000fcec vaddr 0x00007cec paddr 0x00007cec align 2**2
filesz 0x00000008 memsz 0x00000008 flags r--
LOAD off 0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**15
filesz 0x00007cf4 memsz 0x00007cf4 flags r-x
LOAD off 0x00010000 vaddr 0x1fff8000 paddr 0x00007cf4 align 2**15
filesz 0x0000087c memsz 0x00001204 flags rw-
private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point]
Sections:
Idx Name Size VMA LMA File off Algn Flags
0 .isr_vector 00000100 00000000 00000000 00008000 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00007110 00000100 00000100 00008100 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000adc 00007210 00007210 0000f210 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.exidx 00000008 00007cec 00007cec 0000fcec 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA
4 .data 0000087c 1fff8000 00007cf4 00010000 2**3 CONTENTS, ALLOC, LOAD, DATA
5 .bss 00000988 1fff887c 00008570 0001087c 2**2 ALLOC
6 .heap 00002000 1fff9208 1fff9208 00010880 2**3 CONTENTS
7 .stack 00008000 1fff9208 1fff9208 00012880 2**3 CONTENTS
8 .comment 00000070 00000000 00000000 0001a880 2**0 CONTENTS, READONLY
9 .ARM.attributes 00000029 00000000 00000000 0001a8f0 2**0 CONTENTS, READONLY
SYMBOL TABLE:
no symbols
Disassembly of section .text:
00000100 <.text>:
100: d064f8df ldrdle pc, [r4], #-143 ; 0xffffff71 ; <UNPREDICTABLE>
104: 491a4819 ldmdbmi sl, {r0, r3, r4, fp, lr}
108: f04f4a1a ; <UNDEFINED> instruction: 0xf04f4a1a
10c: 42930300 addsmi r0, r3, #0, 6
110: 680cd208 stmdavs ip, {r3, r9, ip, lr, pc}
114: f1006004 ; <UNDEFINED> instruction: 0xf1006004
118: f1010004 setend le
11c: f1030104 ; <UNDEFINED> instruction: 0xf1030104
120: e7f40304 ldrb r0, [r4, r4, lsl #6]!
124: 4a154814 bmi 0x55217c
128: 0300f04f movweq pc, #79 ; 0x4f ; <UNPREDICTABLE>
12c: 0400f04f streq pc, [r0], #-79 ; 0x4f
130: d2054293 andle r4, r5, #805306377 ; 0x30000009
134: f1036004 ; <UNDEFINED> instruction: 0xf1036004
138: f1000304 ; <UNDEFINED> instruction: 0xf1000304
13c: e7f70004 ldrb r0, [r7, r4]!
140: 4a10480f bmi 0x412184
144: 0300f04f movweq pc, #79 ; 0x4f ; <UNPREDICTABLE>
148: 0400f04f streq pc, [r0], #-79 ; 0x4f
14c: d2054293 andle r4, r5, #805306377 ; 0x30000009
150: f1036004 ; <UNDEFINED> instruction: 0xf1036004
154: f1000304 ; <UNDEFINED> instruction: 0xf1000304
158: e7f70004 ldrb r0, [r7, r4]!
15c: 4780480a strmi r4, [r0, sl, lsl #16]
160: 4780480a strmi r4, [r0, sl, lsl #16]
164: 4700480a strmi r4, [r0, -sl, lsl #16]
168: 20008000 andcs r8, r0, r0
16c: 1fff8000 svcne 0x00ff8000
170: 00007cf4 strdeq r7, [r0], -r4
174: 0000087c andeq r0, r0, ip, ror r8
178: 1fff887c svcne 0x00ff887c
17c: 00000988 andeq r0, r0, r8, lsl #19
180: 1fff9208 svcne 0x00ff9208
184: 00002000 andeq r2, r0, r0
188: 000026d9 ldrdeq r2, [r0], -r9
18c: 0000264d andeq r2, r0, sp, asr #12
190: 000001f9 strdeq r0, [r0], -r9
194: 8000f3af andhi pc, r0, pc, lsr #7
198: f0204668 ; <UNDEFINED> instruction: 0xf0204668
19c: 468d0107 strmi r0, [sp], r7, lsl #2
1a0: 4a07b501 bmi 0x1ed5ac
1a4: 78132000 ldmdavc r3, {sp}
1a8: 33014601 movwcc r4, #5633 ; 0x1601
1ac: 7013b2db ; <UNDEFINED> instruction: 0x7013b2db
1b0: f0004a04 ; <UNDEFINED> instruction: 0xf0004a04
1b4: e8bdfa19 pop {r0, r3, r4, r9, fp, ip, sp, lr, pc}
1b8: 46854001 strmi r4, [r5], r1
1bc: bf004770 svclt 0x00004770
1c0: 1fff887c svcne 0x00ff887c
1c4: 00007210 andeq r7, r0, r0, lsl r2
1c8: f0204668 ; <UNDEFINED> instruction: 0xf0204668
1cc: 468d0107 strmi r0, [sp], r7, lsl #2
1d0: 4a07b501 bmi 0x1ed5dc
1d4: 78132001 ldmdavc r3, {r0, sp}
1d8: 33012100 movwcc r2, #4352 ; 0x1100
1dc: 7013b2db ; <UNDEFINED> instruction: 0x7013b2db
1e0: f0004a04 ; <UNDEFINED> instruction: 0xf0004a04
1e4: e8bdfa01 pop {r0, r9, fp, ip, sp, lr, pc}
1e8: 46854001 strmi r4, [r5], r1
1ec: bf004770 svclt 0x00004770
1f0: 1fff887d svcne 0x00ff887d
1f4: 0000721a andeq r7, r0, sl, lsl r2
1f8: ffe0f001 ; <UNDEFINED> instruction: 0xffe0f001
1fc: b1804603 orrlt r4, r0, r3, lsl #12
200: 4a082100 bmi 0x208608
204: f0002002 ; <UNDEFINED> instruction: 0xf0002002
208: f3bff9ef vtbx.8 d15, {d31-<overflow reg d32}, d31
20c: 49068f4f stmdbmi r6, {r0, r1, r2, r3, r6, r8, r9, sl, fp, pc}
210: 68ca4b06 stmiavs sl, {r1, r2, r8, r9, fp, lr}^
214: 62e0f402 rscvs pc, r0, #33554432 ; 0x2000000
218: 60cb4313 sbcvs r4, fp, r3, lsl r3
21c: 8f4ff3bf svchi 0x004ff3bf
220: bf00e7fe svclt 0x0000e7fe
224: 00007223 andeq r7, r0, r3, lsr #4
228: e000ed00 and lr, r0, r0, lsl #26
22c: 05fa0004 ldrbeq r0, [sl, #4]!
230: 4b17b508 blmi 0x5ed658
234: f8b32005 ; <UNDEFINED> instruction: 0xf8b32005
238: f36f2204 vhsub.u32 d18, d15, d4
23c: f8a3220f ; <UNDEFINED> instruction: 0xf8a3220f
240: f8b32204 ; <UNDEFINED> instruction: 0xf8b32204
244: f0422404 ; <UNDEFINED> instruction: 0xf0422404
248: f8a30240 ; <UNDEFINED> instruction: 0xf8a30240
24c: f8b32404 ; <UNDEFINED> instruction: 0xf8b32404
250: f0422404 ; <UNDEFINED> instruction: 0xf0422404
254: f8a30280 ; <UNDEFINED> instruction: 0xf8a30280
258: f8b32404 ; <UNDEFINED> instruction: 0xf8b32404
25c: f36f2404 vshl.u32 d18, d4, d15
260: f8a31245 ; <UNDEFINED> instruction: 0xf8a31245
264: f0012404 ; <UNDEFINED> instruction: 0xf0012404
268: 2200fee8 andcs pc, r0, #232, 28 ; 0xe80
26c: f8d34b08 ; <UNDEFINED> instruction: 0xf8d34b08
270: 04091304 streq r1, [r9], #-772 ; 0x304
274: 3201d504 andcc sp, r1, #4, 10 ; 0x1000000
278: 020cf3c2 andeq pc, ip, #134217731 ; 0x8000003
27c: d1f52a00 mvnsle r2, r0, lsl #20
280: 2204f8b3 andcs pc, r4, #11730944 ; 0xb30000
284: 427ff442 rsbsmi pc, pc, #1107296256 ; 0x42000000
288: 2204f8a3 andcs pc, r4, #10682368 ; 0xa30000
28c: bf00bd08 svclt 0x0000bd08
290: 40033000 andmi r3, r3, r0
294: b5382800 ldrlt r2, [r8, #-2048]! ; 0x800
298: 2580bf0c strcs fp, [r0, #3852] ; 0xf0c
29c: b1092584 smlabblt r9, r4, r5, r2
2a0: 0501f045 streq pc, [r1, #-69] ; 0x45
2a4: f7ff4c15 ; <UNDEFINED> instruction: 0xf7ff4c15
2a8: f8b4ffc3 ; <UNDEFINED> instruction: 0xf8b4ffc3
2ac: 20053404 andcs r3, r5, r4, lsl #8
2b0: 1386f36f orrne pc, r6, #-1140850687 ; 0xbc000001
2b4: 3404f8a4 strcc pc, [r4], #-2212 ; 0x8a4
2b8: 3404f8b4 strcc pc, [r4], #-2228 ; 0x8b4
2bc: 1345f36f movtne pc, #21359 ; 0x536f ; <UNPREDICTABLE>
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So what does this mean. I can't find any useful information about these comments.
ThanX for the Answers
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